Mechanisms for forming gate dielectric layer

ABSTRACT

Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a nitride buffer layer over the semiconductor substrate, and the nitride buffer layer is in an amorphous state. The semiconductor device also includes a crystalline gate dielectric layer over the nitride buffer layer and a gate electrode over the crystalline gate dielectric layer.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapidgrowth. Technological advances in IC materials and design have producedgenerations of ICs. Each generation has smaller and more complexcircuits than the previous generation.

Size reduction of the metal-oxide-semiconductor field-effect transistor(MOSFET) has enabled the continued improvement in speed performance,density, and cost per unit function of integrated circuits over the pastfew decades. As the MOSFET scaling down process continues, the area ofthe gate dielectric layer of the MOSFET is scaled down as well. Therelationship between the gate capacitance (C), the dielectric constant(∈, which is also called the permittivity), the area (A) and thephysical thickness (T) of the gate dielectric layer are shown in Formula(1):

$\begin{matrix}{C = {\frac{ɛ \times A}{T}.}} & {{Formula}\mspace{14mu}(1)}\end{matrix}$

As shown in Formula (1), the scaling down of the area (A) of the gatedielectric layer reduces the gate capacitance (C). Since the performance(i.e. drain saturation currents) of the MOSFET is proportional to thegate capacitance (C), the performance is reduced as the gate capacitance(C) is reduced.

The gate capacitance and the performance may be maintained by thescaling down of the thickness of the gate dielectric layers. However,the scaling down of the gate dielectric thickness results in a largegate leakage current.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the embodiments, and the advantagesthereof, reference is now made to the following descriptions taken inconjunction with the accompanying drawings.

FIG. 1 is a cross-sectional view of an intermediate stage of a processfor forming a semiconductor device, in accordance with some embodiments.

FIG. 2 is a cross-sectional view of an intermediate stage of a processfor forming a semiconductor device, in accordance with some embodiments.

FIG. 3 is a cross-sectional view of an intermediate stage of a processfor forming a semiconductor device, in accordance with some embodiments.

FIGS. 4A-4E are cross-sectional views of various stages of a process forforming a semiconductor device, in accordance with some embodiments.

FIG. 5 is a perspective view of a planar field effect transistor (planarFET), in accordance with some embodiments.

FIG. 6 is a perspective view of a fin field effect transistor (Fin-FET),in accordance with some embodiments.

FIG. 7 is a perspective view of a bulk fin field effect transistor (BulkFin-FET), in accordance with some embodiments.

DETAILED DESCRIPTION OF THE ILLUSTRATIVE EMBODIMENTS

The making and using of the embodiments of the disclosure are discussedin detail below. It should be appreciated, however, that the embodimentscan be embodied in a wide variety of specific contexts. The specificembodiments discussed are merely illustrative, and do not limit thescope of the disclosure.

It is to be understood that the following disclosure provides manydifferent embodiments, or examples, for implementing different featuresof the disclosure. Specific examples of components and arrangements aredescribed below to simplify the present disclosure. These are, ofcourse, merely examples and are not intended to be limiting. Moreover,the performance of a first process before a second process in thedescription that follows may include embodiments in which the secondprocess is performed immediately after the first process, and may alsoinclude embodiments in which additional processes may be performedbetween the first and second processes. Various features may bearbitrarily drawn in different scales for the sake of simplicity andclarity. Furthermore, the formation of a first feature over or on asecond feature in the description that follows include embodiments inwhich the first and second features are formed in direct contact, andmay also include embodiments in which additional features may be formedbetween the first and second features, such that the first and secondfeatures may not be in direct contact.

Some variations of the embodiments are described. Throughout the variousviews and illustrative embodiments, like reference numbers are used todesignate like elements.

The relationship between the gate capacitance (C), the area (A), thedielectric constant (∈_(SiO2)) and the physical thickness (T_(SiO2)) ofa SiO₂ gate dielectric layer, the dielectric constant (∈_(HK)), thephysical thickness (T_(HK)) and the equivalent oxide thickness(EOT_(HK)) of a high-k (or high-∈) metal oxide gate dielectric layer(with a dielectric constant higher than that of silicon dioxides) areshown in Formula (2):

$\begin{matrix}{C = {\frac{ɛ_{{SiO}\; 2} \times A}{T_{{SiO}\; 2}} = {\frac{ɛ_{HK} \times A}{T_{HK}} = {\frac{ɛ_{{SiO}\; 2} \times A}{{EOT}_{HK}}.}}}} & {{Formula}\mspace{14mu}(2)}\end{matrix}$

According to Formula (2), since the dielectric constant of metal oxidematerial is greater than that of silicon dioxides, the metal oxidematerials have been proposed as potential gate dielectric materials. Thehigh-k metal oxide gate dielectric layer allows for a larger physicalthickness (compared to SiO₂) for obtaining a same gate capacitance thatcan be obtained with a much thinner SiO₂ gate dielectric layer. Thelarger physical thickness of the high-k metal oxide gate dielectriclayer can reduce gate leakage currents. High-k metal oxide materialsinclude, for example, aluminum oxide (Al₂O₃).

FIG. 1 is a cross-sectional view of an intermediate stage of a processfor forming a semiconductor device, in accordance with some embodiments.As shown in FIG. 1, a semiconductor substrate 110 is provided. A silicondioxide buffer layer 120 and a gate dielectric layer 130 are formed onthe semiconductor substrate 110 sequentially. The gate dielectric layer130 is an amorphous dielectric layer, which is made of aluminum oxide.Since the gate dielectric layer 130 is in the amorphous state, the gatedielectric layer 130 may not have a sufficient dielectric constant tomaintain the gate capacitance and the performance in a suitable range.

To solve the problem mentioned above, the structure in FIG. 1 may beannealed to crystallize the gate dielectric layer 130 into acrystallized gate dielectric layer 130 a, as shown in FIG. 2. Thecrystallized gate dielectric layer 130 a has a higher dielectricconstant and a lower equivalent oxide thickness than that of the gatedielectric layer 130. However, the crystallized gate dielectric layer130 a results in a large gate leakage current.

To solve the problem mentioned above, a nitrogen plasma treatment isperformed on the crystallized gate dielectric layer 130 a to lower thecrystallinity of the crystallized gate dielectric layer 130 a, as shownin FIG. 3. However, since the crystallinity of the crystallized gatedielectric layer 130 a is lowered, the dielectric constant is loweredand the equivalent oxide thickness is increased. As a result, the gatecapacitance and the performance are low.

Therefore, it is desired to find alternative mechanisms for forming agate dielectric layer, which has a high dielectric constant and a lowequivalent oxide thickness and is able to reduce the gate leakagecurrent.

FIGS. 4A-4E are cross-sectional views of various stages of a process forforming a semiconductor device, in accordance with some embodiments.Referring to FIG. 4A, a semiconductor substrate 410 is provided. Thesemiconductor substrate 410 may be a semiconductor wafer (such as asilicon wafer) or a portion of a semiconductor wafer.

In some embodiments, the semiconductor substrate 410 is made of anelementary semiconductor material including silicon or germanium in asingle crystal, polycrystal, or amorphous structure. In some otherembodiments, the semiconductor substrate 410 is made of a compoundsemiconductor, such as silicon carbide, gallium arsenide, galliumphosphide, indium phosphide, indium arsenide, an alloy semiconductor,such as SiGe, or GaAsP, or combinations thereof.

The semiconductor substrate 410 may also include multi-layersemiconductors, semiconductor on insulator (SOI) (such as silicon oninsulator or germanium on insulator), or combinations thereof. Thesemiconductor substrate 410 may be treated by a chemical cleaningprocess and/or a dipping process with a hydrofluoric acid.

Afterwards, a buffer layer (also referred to as an interfacial layer)420 is formed over the semiconductor substrate 410. In some embodiments,the buffer layer 420 is in direct contact with the semiconductorsubstrate 410. In some embodiments, the buffer layer 420 is made of(high-k) dielectric materials with a dielectric constant higher thanthat of silicon dioxides. For example, the buffer layer 420 is made ofmetal oxides, such as aluminum oxides (Al₂O₃), cerium oxides (CeO₂),hafnium aluminum oxides (HfAlO), lanthanum aluminum oxides (LaAlO₃) orother suitable high-k metal oxide materials.

The buffer layer 420 is deposited by using a chemical vapor deposition(CVD) process, an atomic layer deposition (ALD) process or othersuitable deposition processes. In some embodiments, the ALD processincludes a remote plasma atomic layer deposition (RP-ALD) process.

The deposition temperature of the buffer layer 420 may range from about50° C. to about 450° C. In some embodiments, the buffer layer 420includes aluminum oxides, and the deposition temperature may be about250° C. The buffer layer 420 is in an amorphous state, in accordancewith some embodiments. In some other embodiments, the buffer layer 420is made of silicon dioxides.

Then, as shown in FIG. 4B, a nitridation process is performed on thebuffer layer 420 to convert the buffer layer 420 into a nitride bufferlayer 490 a. The nitridation process includes a nitrogen plasmatreatment (e.g. a remote nitrogen plasma treatment) or other suitablenitridation treatments. The nitridation process may be performed byapplying an ammonia gas (NH₃) at a flow rate of 20 sccm (standard cubiccentimeters per minute) at 250° C. for 3 minutes.

The nitride buffer layer 420 a may have a higher dielectric constantthan that of the buffer layer 420. The nitridation process may reducethe gate leakage current by filling the oxygen vacancies in the bufferlayer 420 with nitrogen. Furthermore, the nitrogen in the nitride bufferlayer 420 a may prevent the nitride buffer layer 420 a from beingconverted from the amorphous state into a crystalline state insubsequent annealing processes. Therefore, the nitride buffer layer 420a in the amorphous state may effectively reduce the gate leakagecurrent.

Besides, the nitrogen ions in the nitride buffer layer 420 a may reactwith the semiconductor substrate 410 to form an interfacial layer (notshown) between the nitride buffer layer 420 a and the semiconductorsubstrate 410. The interfacial layer includes, for example, a siliconnitride film. The interfacial layer may prevent the oxygen in thenitride buffer layer 420 a from reacting with the semiconductorsubstrate 410, which avoids forming an undesired oxide film (i.e. alow-k film) between the nitride buffer layer 420 a and the semiconductorsubstrate 410.

Afterwards, as shown in FIG. 4C, a gate dielectric layer 430 isdeposited over the nitride buffer layer 420 a. In some embodiments, thegate dielectric layer 430 is in direct contact with the nitride bufferlayer 420 a. The gate dielectric layer 430 is made of high-k metal oxidematerials, such as zirconium oxides (ZrO₂), gadolinium oxides (Gd₂O₃),hafnium oxides (HfO₂), barium titanium oxides (BaTiO₃) or aluminumoxides (Al₂O₃).

In some embodiments, the gate dielectric layer 430 includes zirconiumoxides, and the buffer layer 420 (or the nitride buffer layer 420 a)includes aluminum oxides. In some embodiments, the gate dielectric layer430 has a dielectric constant higher than that of the nitride bufferlayer 420 a (or the buffer layer 420). For example, the dielectricconstant of the gate dielectric layer 430 is in a range from about 9 toabout 80.

The gate dielectric layer 430 is deposited by using a chemical vapordeposition (CVD) process, an atomic layer deposition (ALD) process orother suitable deposition processes. In some embodiments, the ALDprocess includes a remote plasma atomic layer deposition (RP-ALD)process. In some embodiments, the deposition temperature of the gatedielectric layer 430 may range from about 50° C. to about 450° C. Insome embodiments, the gate dielectric layer 430 includes zirconiumoxides, and the deposition temperature of the gate dielectric layer 430may be about 250° C.

Afterwards, as shown in FIG. 4D, a thermal annealing process isperformed to crystallize the gate dielectric layer 430 into acrystalline gate dielectric layer 430 a. The crystalline gate dielectriclayer 430 a has a higher dielectric constant and a lower equivalentoxide thickness than that of the gate dielectric layer 430 in anamorphous state (or in a low crystalline state). Therefore, the gatecapacitance is improved, and the performance of the semiconductor deviceusing the crystalline gate dielectric layer 430 a is improved as well.

In some embodiments, the crystalline gate dielectric layer 430 a (or thegate dielectric layer 430) and the nitride buffer layer 420 a (or thebuffer layer 420) are made of different materials. In some embodiments,the crystalline gate dielectric layer 430 a has a dielectric constanthigher than that of the nitride buffer layer 420 a (or the buffer layer420).

The thermal annealing temperature may range from about 200° C. to about1000° C. In some embodiments, the gate dielectric layer 430 includingzirconium oxides may be annealed at about 450° C. to be crystallizedinto the crystalline gate dielectric layer 430 a having a tetragonalphase. The crystalline gate dielectric layer 430 a with the tetragonalphase has a high dielectric constant ranging from, for example, about 40to about 50.

The thickness T1 of the nitride buffer layer 420 a may range from 0.1 nmto several nm. In some embodiments, the nitride buffer layer 420 a ismade of aluminum oxides, and the thickness T1 is about 1 nm. Thethickness T2 of the crystalline gate dielectric layer 430 a may rangefrom 0.2 nm to several nm. In some embodiments, the crystalline gatedielectric layer 430 a is made of zirconium oxides, and the thickness T2is about 5.5 nm. In some embodiments, the thickness T2 is larger thanthe thickness T1.

In some embodiments, the nitrogen in the nitride buffer layer 420 a mayprevent (or inhibit) the nitride buffer layer 420 a from being convertedinto a crystalline state. Therefore, the nitride buffer layer 420 a isstill in a substantially amorphous state after the thermal annealingprocess, and the nitride buffer layer 420 a after the thermal annealingprocess is able to effectively reduce the gate leakage current.

In some embodiments, the thermal annealing temperature is lower than thecrystallization temperature of the nitride buffer layer 420 a to preventthe nitride buffer layer 420 a from being crystallized. That is, thecrystallization temperature of the gate dielectric layer 430 may belower than that of the nitride buffer layer 420 a.

Then, referring to FIG. 4E, a gate electrode 440 is deposited over thecrystalline gate dielectric layer 430 a. The gate electrode 440 is madeof polysilicon, metal materials or alloy materials, in accordance withsome embodiments. The metal materials of the gate electrode 440 mayinclude aluminum, tungsten, gold, platinum, cobalt, other suitablemetals, alloys thereof, or combinations thereof. The gate electrode 440may be deposited by using a PVD process, a CVD process, a platingprocess, a sputtering process, the like, or combinations thereof.

The nitride buffer layer 420 a and the crystalline gate dielectric layer430 a may be used in various transistors. Some of the transistors areexemplarily illustrated as follows, but the present disclosure is notlimited thereto.

FIG. 5 is a perspective view of a planar field effect transistor (planarFET), in accordance with some embodiments. As shown in FIG. 5, a planarfield effect transistor 500 includes the semiconductor substrate 410,the nitride buffer layer 420 a, the crystalline gate dielectric layer430 a, the gate electrode 440, a source 450 and a drain 460, inaccordance with some embodiments.

In some embodiments, the semiconductor substrate 410 is a semiconductoron insulator (SOI) substrate. The semiconductor substrate 410 mayinclude a bottom bulk semiconductor layer 410 a (also referred to as“bulk” or “bulk layer”), a buried insulating layer 410 b (also referredto as “BOX”), and a semiconductor layer 410 c (also referred to as “SOI”or “SOI layer”) over the top of the buried insulating layer 410 b.Alternatively, in some other embodiments, the semiconductor substrate410 may be a single-layer semiconductor substrate.

The nitride buffer layer 420 a, the crystalline gate dielectric layer430 a and the gate electrode 440 are sequentially formed over thesemiconductor layer 410 c by the methods shown in FIGS. 4A-4E. In someembodiments, spacers 470 are formed over sidewalls of the nitride bufferlayer 420 a, the crystalline gate dielectric layer 430 a and the gateelectrode 440. The spacers 470 may be made of a dielectric material,such as silicon nitrides, silicon oxynitrides, or combinations thereof.In some embodiments, lightly doped regions 480 are formed in thesemiconductor layer 410 c and are located under the spacers 470 and thenitride buffer layer 420 a.

The source 450 and the drain 460 are formed over the buried insulatinglayer 410 b and are formed at two opposite sides of the gate electrode440, in accordance with some embodiments. That is, the nitride bufferlayer 420 a, the crystalline gate dielectric layer 430 a and the gateelectrode 440 are located between the source 450 and the drain 460. Thespacers 470 separate the gate electrode 440 from the source 450 and thedrain 460.

FIG. 6 is a perspective view of a fin field effect transistor (Fin-FET),in accordance with some embodiments. As shown in FIG. 6, a fin fieldeffect transistor 600 includes the semiconductor substrate 410, thenitride buffer layer 420 a, the crystalline gate dielectric layer 430 a,the gate electrode 440, a source region 450 a and a drain region 460 a,in accordance with some embodiments.

In some embodiments, the semiconductor substrate 410 is a semiconductoron insulator (SOI) substrate. The semiconductor substrate 410 mayinclude a bottom bulk semiconductor layer 410 a, a buried insulatinglayer 410 b, and a semiconductor layer (also referred to as “SOI” or“SOI layer”) 410 c on the top of the buried insulating layer 410 b. Thesemiconductor layer 410 c is a fin-shaped structure. The source region450 a and the drain region 460 a are formed in the semiconductor layer410 c.

The nitride buffer layer 420 a, the crystalline gate dielectric layer430 a and the gate electrode 440 are sequentially formed over thesidewalls 410 d and the top surface 410 e of the semiconductor layer 410c by the methods shown in FIGS. 4A-4E. The nitride buffer layer 420 a,the crystalline gate dielectric layer 430 a, the gate electrode 440 arelocated between the source region 450 a and the drain region 460 a.

FIG. 7 is a perspective view of a bulk fin field effect transistor (BulkFin-FET), in accordance with some embodiments. As shown in FIG. 7, abulk fin field effect transistor 700 includes the semiconductorsubstrate 410, the nitride buffer layer 420 a, the crystalline gatedielectric layer 430 a, the gate electrode 440, a source region 450 a, adrain region 460 a and an insulating layer 710, in accordance with someembodiments.

In some embodiments, the semiconductor substrate 410 is a bulksemiconductor substrate. The semiconductor substrate 410 may include asemiconductor layer 410 f and a fin-shaped structure 410 g over a topsurface 412 f of the semiconductor layer 410 f. The source region 450 aand the drain region 460 a are formed in the fin-shaped structure 410 g.The insulating layer 710 is formed over the top surface 412 f exposed bythe fin-shaped structure 410 g. The insulating layer 710 may include,for example, silicon oxides or silicon nitrides.

The nitride buffer layer 420 a, the crystalline gate dielectric layer430 a and the gate electrode 440 are sequentially formed over thesidewalls 410 h and the top surface 410 i of the fin-shaped structure410 g by the methods shown in FIGS. 4A-4E. A portion of the nitridebuffer layer 420 a, the crystalline gate dielectric layer 430 a and thegate electrode 440 is located over the insulating layer 710. The nitridebuffer layer 420 a, the crystalline gate dielectric layer 430 a and thegate electrode 440 are located between the source region 450 a and thedrain region 460 a.

Embodiments of mechanisms for forming a semiconductor device describedabove nitride the buffer layer into the nitride buffer layer to reducethe gate leakage current. Furthermore, the embodiments of the mechanismscrystallize the gate dielectric layer into the crystalline gatedielectric layer to increase the dielectric constant and to lower theequivalent oxide thickness. Due to the nitrogen in the nitride bufferlayer may inhibit the crystallization of the nitride buffer layer duringthe crystallization of the gate dielectric layer, the nitride bufferlayer is maintained in the amorphous state and therefore could reducethe gate leakage current. Therefore, the gate capacitance is improved,and the performance of the semiconductor device using the crystallinegate dielectric layer is improved as well.

In accordance with some embodiments, a semiconductor device is provided.The semiconductor device includes a semiconductor substrate and anitride buffer layer over the semiconductor substrate, wherein thenitride buffer layer is in an amorphous state. The semiconductor devicealso includes a crystalline gate dielectric layer over the nitridebuffer layer and a gate electrode over the crystalline gate dielectriclayer.

In accordance with some embodiments, a semiconductor device is provided.The semiconductor device includes a semiconductor substrate and anitride buffer layer over the semiconductor substrate, wherein thenitride buffer layer is in an amorphous state. The nitride buffer layerhas a dielectric constant larger than that of silicon dioxides. Thesemiconductor device also includes a crystalline gate dielectric layerover the nitride buffer layer and a gate electrode over the crystallinegate dielectric layer.

In accordance with some embodiments, a method for forming asemiconductor device is provided. The method includes providing asemiconductor substrate and forming a buffer layer over thesemiconductor substrate, wherein the buffer layer is in an amorphousstate. The method also includes nitriding the buffer layer into anitride buffer layer and forming a gate dielectric layer over thenitride buffer layer. The method further includes performing a thermalannealing process to crystallize the gate dielectric layer into acrystalline gate dielectric layer and forming a gate electrode over thecrystalline gate dielectric layer.

Although the embodiments and their advantages have been described indetail, it should be understood that various changes, substitutions, andalterations can be made herein without departing from the spirit andscope of the embodiments as defined by the appended claims. Moreover,the scope of the present application is not intended to be limited tothe particular embodiments of the process, machine, manufacture,composition of matter, means, methods, and steps described in thespecification. As one of ordinary skill in the art will readilyappreciate from the disclosure, processes, machines, manufacture,compositions of matter, means, methods, or steps, presently existing orlater to be developed, that perform substantially the same function orachieve substantially the same result as the corresponding embodimentsdescribed herein may be utilized according to the disclosure.Accordingly, the appended claims are intended to include within theirscope such processes, machines, manufacture, compositions of matter,means, methods, or steps. In addition, each claim constitutes a separateembodiment, and the combination of various claims and embodiments arewithin the scope of the disclosure.

What is claimed is:
 1. A semiconductor device, comprising: asemiconductor substrate; a nitride buffer layer over the semiconductorsubstrate, wherein the nitride buffer layer is in an amorphous state; acrystalline gate dielectric layer over the nitride buffer layer; and agate electrode over the crystalline gate dielectric layer.
 2. Thesemiconductor device as claimed in claim 1, wherein the nitride bufferlayer comprises metal oxides.
 3. The semiconductor device as claimed inclaim 2, wherein the nitride buffer layer comprises aluminum oxides,cerium oxides, hafnium aluminum oxides, lanthanum aluminum oxides andcombinations thereof.
 4. The semiconductor device as claimed in claim 1,wherein the crystalline gate dielectric layer and the nitride bufferlayer are made of different materials.
 5. The semiconductor device asclaimed in claim 1, wherein the crystalline gate dielectric layer has adielectric constant higher than that of the nitride buffer layer.
 6. Thesemiconductor device as claimed in claim 1, wherein the crystalline gatedielectric layer comprises a first metal oxide, and the nitride bufferlayer comprises a second metal oxide, which is different from the firstmetal oxide.
 7. The semiconductor device as claimed in claim 1, whereinthe crystalline gate dielectric layer comprises zirconium oxides, andthe nitride buffer layer comprises aluminum oxides.
 8. The semiconductordevice as claimed in claim 1, further comprising: a source over thesemiconductor substrate; and a drain over the semiconductor substrate,wherein the nitride buffer layer, the crystalline gate dielectric layerand the gate electrode are between the source and the drain.
 9. Thesemiconductor device as claimed in claim 1, wherein the semiconductorsubstrate is a semiconductor on insulator substrate, the semiconductorsubstrate comprises a semiconductor on insulator layer with a fin shape,a source region and a drain region are in the semiconductor on insulatorlayer, wherein the nitride buffer layer, the crystalline gate dielectriclayer and the gate electrode are over sidewalls and a top surface of thesemiconductor on insulator layer and are between the source region andthe drain region.
 10. The semiconductor device as claimed in claim 1,wherein the semiconductor substrate is a bulk semiconductor substrateand has a fin-shaped structure, a source region and a drain region arein the fin-shaped structure, wherein the nitride buffer layer, thecrystalline gate dielectric layer and the gate electrode are oversidewalls and a top surface of the fin-shaped structure and are betweenthe source region and the drain region.
 11. A semiconductor device,comprising: a semiconductor substrate; a nitride buffer layer over thesemiconductor substrate, wherein the nitride buffer layer is in anamorphous state, and the nitride buffer layer has a dielectric constantlarger than that of silicon dioxides; a crystalline gate dielectriclayer over the nitride buffer layer; and a gate electrode over thecrystalline gate dielectric layer.
 12. The semiconductor device asclaimed in claim 11, wherein the crystalline gate dielectric layercomprises zirconium oxides with a tetragonal phase.
 13. Thesemiconductor device as claimed in claim 11, wherein the crystallinegate dielectric layer has a dielectric constant higher than that of thenitride buffer layer.
 14. The semiconductor device as claimed in claim13, wherein the crystalline gate dielectric layer comprises gadoliniumoxides, hafnium oxides, barium titanium oxides, aluminum oxides,zirconium oxides or combinations thereof.
 15. The semiconductor deviceas claimed in claim 11, wherein the nitride buffer layer comprises metaloxides.
 16. The semiconductor device as claimed in claim 15, wherein thenitride buffer layer comprises aluminum oxides, cerium oxides, hafniumaluminum oxides, lanthanum aluminum oxides and combinations thereof. 17.The semiconductor device as claimed in claim 11, wherein the crystallinegate dielectric layer and the nitride buffer layer are made of differentmaterials.
 18. The semiconductor device as claimed in claim 11, whereinthe crystalline gate dielectric layer comprises a first metal oxide, andthe nitride buffer layer comprises a second metal oxide, which isdifferent from the first metal oxide.
 19. The semiconductor device asclaimed in claim 11, wherein the crystalline gate dielectric layercomprises zirconium oxides, and the nitride buffer layer comprisesaluminum oxides.
 20. The semiconductor device as claimed in claim 11,wherein the semiconductor substrate is a bulk semiconductor substrateand has a fin-shaped structure, a source region and a drain region arein the fin-shaped structure, wherein the nitride buffer layer, thecrystalline gate dielectric layer and the gate electrode are oversidewalls and a top surface of the fin-shaped structure and are betweenthe source region and the drain region.